This application relates in general to a method, apparatus, and article of manufacture for providing high speed digital communications through a communications channel, and more particularly to a method, apparatus, and article of manufacture for providing a variable delay finite impulse response equalizer for baseband communications.
Digital communications systems are continuously increasing the transfer rate at which data is transmitted between devices through a communications channel, for example, a backplane. To meet that increase, conventional systems have employed certain techniques of increasing the rate of the transmitted signal or increasing the number of bits per symbol while maintaining the transmission rate. The first approach is problematic in that most distortions that plague communications systems increase with increasing frequency and thus the fidelity of the received signal is degraded. The second approach is also problematic because the voltage margin is reduced when including more information per transmitted symbol. The result is that either approach may require an improvement in received signal quality to maintain a given quality of service.
A common approach to address this situation is to utilize an equalizer (adaptive or otherwise) to compensate for the increased distortion and/or the increased sensitivity to distortion. However, including an equalizer adds cost, complexity and power consumption to a receiver or transceiver. Thus, there is a strong desire to develop an equalizer structure that can provide the required compensation with a minimum of complexity.
Typically, a conventional symbol spaced equalizer implemented as a discrete-time system can correct for a channel pulse response duration or length of N*Tsym seconds, where N is the number of taps of the equalizer and Tsym is the symbol period. A fractionally spaced equalizer implemented as a discrete-time system can correct for a channel pulse response duration or length of N*Ttap seconds, where N is the number of taps of the equalizer and Ttap is the tap period which is a fraction of a symbol period.
However, in certain situations, a subset of the taps in the equalizer may be zero. One such situation may occur in systems in which daughter cards are plugged into a motherboard. Thus, it may be desirable to eliminate the circuitry for taps that would converge to zero. However, after design and manufacture, conventional symbol spaced equalizers have limited flexibility when implemented within a particular environment.
Thus, there is a need for an improved variable equalizer in order to enhance the system performance of, for example, high-speed digital communications through a communications channel, for example a backplane. There is a need for an equalizer with improved flexibility and spanning a large time range without requiring the circuitry and complexity of the intermediate taps that may not be used in a given situation.